The successive over-relaxation method in reconfigurable hardware

Safaa J. Kasbah, Ramzi A. Haraty, Issam W. Damaj

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This paper presents the first hardware implementation of the Successive Over-Relaxation (SOR) method for the solution of a 2D Poisson equation. We use Handel-C, a high level language for the implementation of algorithms on hardware, to code and implement our design which we map onto high-performance Field Programmable Gate Arrays (FPGAs), such as, Virtex II Pro, Altera Stratix, and Spartan3L. We use the FPGA vendors' proprietary software to analyze the design implementation performance. Besides, we implement SOR using C++ and compare our timing results with the obtained C++ version results. Our findings prove that SOR in hardware outperforms SOR in software.

Original languageEnglish
Title of host publicationIMECS 2007 - International MultiConference of Engineers and Computer Scientists 2007
Pages2395-2400
Number of pages6
Publication statusPublished - 2007
Externally publishedYes
EventInternational MultiConference of Engineers and Computer Scientists 2007, IMECS 2007 - Kowloon, Hong Kong
Duration: 21 Mar 200723 Mar 2007

Publication series

NameLecture Notes in Engineering and Computer Science
ISSN (Print)2078-0958

Conference

ConferenceInternational MultiConference of Engineers and Computer Scientists 2007, IMECS 2007
Country/TerritoryHong Kong
CityKowloon
Period21/03/0723/03/07

Keywords

  • Hardware Design
  • High Performance Computing
  • Iterative Methods
  • Parallelization

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