Prototyping using multi-FPGA platform: A novel and complete flow

Multi-FPGA prototyping platforms have seen tremendous popularity in recent times. This is because of the fact that they offer significant advantages like better speed and real world testing experience as compared to other prototyping techniques like simulation and emulation-based prototyping. However, a major challenge hampering the rapid evolution of multi-FPGA platforms is the absence of a complete and efficient back-end academic flow. Some commercial flows exist. But they are expensive and platform dependent. There exist some academic solutions as well. But most of them offer partial solutions only. In this work, we present a novel back-end flow for multi-FPGA prototyping. The major contribution of this flow is that it offers complete prototyping experience and all the tools used in this flow are either free for academia or developed by the academia. We perform extensive experimentation and exploration using the proposed flow. For experimentation, we use a set of fourteen mono- and multi-cluster benchmarks. These benchmarks are passed through all the steps of multi-FPGA prototyping. During exploration, we put special emphasis on two important steps of back-end flow. One step is partitioning and the other is routing. For partitioning, we explore two different approaches namely hierarchical and multilevel approach. For routing, we explore two routing approaches namely bi-terminal and multi-terminal routing. Experimental results show that multilevel approach gives 12.5% better cut-net results for mono-cluster benchmarks while hierarchical approach gives 13% better cut-net results for multi-cluster benchmarks. Furthermore, the comparison of bi- and multi-terminal routing approach shows that the latter gives, on average, 11.3% better frequency results as compared to the former.