Parallel on-chip ciphers development for the third generation mobile telecommunication system

The paper focuses on the synthesis of a highly parallel hardware implementation of the main cipher designed for the third generation mobile communication system. The investigated algorithm is the KASUMI block cipher. Currently, KASUMI is well known to be a strong encryption algorithm. The use of such an algorithm within critical applications, such as mobile communication, requires efficient, highly reliable and correct hardware implementation. We will investigate satisfying such requirements by proposing and adopting a step-wise refinement software engineering approach to develop correct hardware circuits. The method uses a formal functional programming notation for specifying algorithms. The parallel behavior is then obtained through the use of a combination of function decomposition strategies, besides, data and process refinement techniques. The refinements are inspired by the operators of Communicating Sequential Processes (CSP) and map easily to programs in Handel-C (a modern C-based high-level langauge with hardware output). In this paper, we obtain several hardware implementations with different performance characteristics by applying different refinements to the algorithm. The developed designs are compiled and tested under Celoxica's RC-1000 reconfigurable computer with its 2 million gates Virtex-E FPGA. Performance analysis and evaluation of these implementations are included.