High speed hardware implementation of a heuristic 2D rectangle placement algorithm

Amina Y. Maarouf; Issam W. Damaj

doi:10.1109/aiccsa.2006.205098

High speed hardware implementation of a heuristic 2D rectangle placement algorithm

Amina Y. Maarouf^*, Issam W. Damaj

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Many areas of industry involve computationally intensive layout design problems. A high performance computing system for swiftly generating and analyzing layout alternatives is much desired. The performance of such a system is largely affected by the efficiency of the placement algorithm and its degree of parallelism, and the employed hardware platform. In this paper, we present parallelization and high speed hardware implementation of a heuristic 2D rectangle placement algorithm. A performance analysis and evaluation of the suggested mapping onto reconfigurable hardware is also presented.

Original language	English
Title of host publication	IEEE International Conference on Computer Systems and Applications, 2006
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	255-261
Number of pages	7
ISBN (Print)	1424402123, 9781424402120
DOIs	https://doi.org/10.1109/aiccsa.2006.205098
Publication status	Published - 18 Apr 2006
Externally published	Yes
Event	IEEE International Conference on Computer Systems and Applications, 2006 - Sharjah, United Arab Emirates Duration: 8 Mar 2006 → 8 Mar 2006

Publication series

Name	IEEE International Conference on Computer Systems and Applications, 2006

Conference

Conference	IEEE International Conference on Computer Systems and Applications, 2006
Country/Territory	United Arab Emirates
City	Sharjah
Period	8/03/06 → 8/03/06

Access to Document

10.1109/aiccsa.2006.205098

Cite this

Maarouf, A. Y., & Damaj, I. W. (2006). High speed hardware implementation of a heuristic 2D rectangle placement algorithm. In IEEE International Conference on Computer Systems and Applications, 2006 (pp. 255-261). Article 1618363 (IEEE International Conference on Computer Systems and Applications, 2006). Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.1109/aiccsa.2006.205098

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title = "High speed hardware implementation of a heuristic 2D rectangle placement algorithm",

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author = "Maarouf, {Amina Y.} and Damaj, {Issam W.}",

year = "2006",

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publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

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note = "IEEE International Conference on Computer Systems and Applications, 2006 ; Conference date: 08-03-2006 Through 08-03-2006",

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Maarouf, AY & Damaj, IW 2006, High speed hardware implementation of a heuristic 2D rectangle placement algorithm. in IEEE International Conference on Computer Systems and Applications, 2006., 1618363, IEEE International Conference on Computer Systems and Applications, 2006, Institute of Electrical and Electronics Engineers (IEEE), pp. 255-261, IEEE International Conference on Computer Systems and Applications, 2006, Sharjah, United Arab Emirates, 8/03/06. https://doi.org/10.1109/aiccsa.2006.205098

High speed hardware implementation of a heuristic 2D rectangle placement algorithm. / Maarouf, Amina Y.; Damaj, Issam W.
IEEE International Conference on Computer Systems and Applications, 2006. Institute of Electrical and Electronics Engineers (IEEE), 2006. p. 255-261 1618363 (IEEE International Conference on Computer Systems and Applications, 2006).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - Many areas of industry involve computationally intensive layout design problems. A high performance computing system for swiftly generating and analyzing layout alternatives is much desired. The performance of such a system is largely affected by the efficiency of the placement algorithm and its degree of parallelism, and the employed hardware platform. In this paper, we present parallelization and high speed hardware implementation of a heuristic 2D rectangle placement algorithm. A performance analysis and evaluation of the suggested mapping onto reconfigurable hardware is also presented.

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Maarouf AY, Damaj IW. High speed hardware implementation of a heuristic 2D rectangle placement algorithm. In IEEE International Conference on Computer Systems and Applications, 2006. Institute of Electrical and Electronics Engineers (IEEE). 2006. p. 255-261. 1618363. (IEEE International Conference on Computer Systems and Applications, 2006). doi: 10.1109/aiccsa.2006.205098

High speed hardware implementation of a heuristic 2D rectangle placement algorithm

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