Graphics algorithms under high performance reconfigurable systems

The rapid progress and advancement in electronic chips technology provides a variety of new implementation options for system engineers. The choice varies between the flexible programs running on a general purpose processor (GPP) and the fixed hardware implementation using an application specific integrated circuit (ASIC). Many other implementation options present, for instance, a system with a RISC processor and a DSP core. Other options include graphics processors and microcontrollers. Specialist processors certainly improve performance over general-purpose ones, but this comes as a quid pro quo for flexibility. Combining the flexibility of GPPs and the high performance of ASICs leads to the introduction of reconfigurable computing (RC) as a new implementation option with a balance between versatility and speed. Field Programmable Gate Arrays (FPGAs), nowadays are important components of RC-systems, have shown a dramatic increase in their density over the last few years. For example, companies like Xilinx [1] and Altera [2] have enabled the production of FPGAs with several millions of gates, such as, the Virtex-2 Pro and the Stratix-2 FPGAs. Considerable research efforts have been made to develop a variety of RC-systems. Research prototypes with fine-grain granularity include Splash [3], DECPeRLe-1 [4], DPGA [5] and Garp [6]. Examples of systems with coarse-grain granularity are RaPiD [7], MorphoSys [8], and RAW [9]. Many other systems were also developed, for instance, rDPA [10], MATRIX [11], REMARC [12], DISC [13], Spyder [14] and PRISM [15]. The focus of this paper is introducing reconfigurable computers as modern supercomputing architectures. The paper also investigates the main reasons behind the current advancement in the development of RC-systems. Furthermore, a technical survey of various RC-systems is included laying common grounds for comparisons. In addition, this paper mainly presents case studies implemented under the MorphoSys RC-system. The selected case studies belong to computer graphics. Parallel versions of the studied algorithms are developed to match the topologies supported by the MorphoSys. Performance evaluation and results analyses are included for implementations with different characteristics.