Abstract
In this brief, we present FracTCAM, an efficient methodology for ternary content addressable memory (TCAM) emulation on Xilinx field-programmable gate arrays (FPGAs) by leveraging primitive architectural resources. The proposed methodology exploits the fracturable nature of lookup table random access memories (LUTRAMs) and built-in slice flip-flops for deeper pipelining. Multiple slices can be combined together to build deeper and wider TCAMs using ANDing operations. This results in TCAM implementations that achieve lower resources utilization, lower delay, and power consumption. A comparison with the existing schemes shows that FracTCAM consistently achieves the best performance per area (PA) and performance per area per watt (PAW).
Original language | English |
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Article number | 9217507 |
Pages (from-to) | 2726-2730 |
Number of pages | 5 |
Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Volume | 28 |
Issue number | 12 |
DOIs | |
Publication status | Published - 8 Oct 2020 |
Externally published | Yes |
Keywords
- Field-programmable gate array (FPGA)
- packet classification
- partial reconfiguration
- ternary content addressable memories (TCAMs)