Co-designs of parallel Rijndael

Issam W. Damaj

doi:10.1109/ISSOC.2011.6089220

Co-designs of parallel Rijndael

Issam W. Damaj^*

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Citation (Scopus)

Abstract

State-of-the-art Field Programmable Gate Arrays (FPGAs) have inspired the innovation of hardware/software co-design methodologies that provide a high-level of abstraction in the design process. In this paper, we explore the effectiveness of a formal methodology in the co-design of parallel versions of the Rijndael cryptographic algorithm. The investigated methodology employs the functional paradigm for specifications, derived concurrency, and hardware mapping. Several implementations are developed with different performance characteristics. The refined designs are tested under RC-1000 reconfigurable computer with its two million gates FPGA.

Original language	English
Title of host publication	2011 International Symposium on System on Chip, SoC 2011
Pages	72-77
Number of pages	6
DOIs	https://doi.org/10.1109/ISSOC.2011.6089220
Publication status	Published - 1 Dec 2011
Externally published	Yes
Event	13th International Symposium on System-on-Chip, SoC 2011 - Tampere, Finland Duration: 31 Oct 2011 → 2 Nov 2011

Conference

Conference	13th International Symposium on System-on-Chip, SoC 2011
Country/Territory	Finland
City	Tampere
Period	31/10/11 → 2/11/11

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10.1109/ISSOC.2011.6089220

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Co-designs of parallel Rijndael

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