The successive over-relaxation method in reconfigurable hardware

Safaa J. Kasbah, Ramzi A. Haraty, Issam W. Damaj

Allbwn ymchwil: Pennod mewn Llyfr/Adroddiad/Trafodion CynhadleddCyfraniad mewn cynhadleddadolygiad gan gymheiriaid

Crynodeb

This paper presents the first hardware implementation of the Successive Over-Relaxation (SOR) method for the solution of a 2D Poisson equation. We use Handel-C, a high level language for the implementation of algorithms on hardware, to code and implement our design which we map onto high-performance Field Programmable Gate Arrays (FPGAs), such as, Virtex II Pro, Altera Stratix, and Spartan3L. We use the FPGA vendors' proprietary software to analyze the design implementation performance. Besides, we implement SOR using C++ and compare our timing results with the obtained C++ version results. Our findings prove that SOR in hardware outperforms SOR in software.

Iaith wreiddiolSaesneg
TeitlIMECS 2007 - International MultiConference of Engineers and Computer Scientists 2007
Tudalennau2395-2400
Nifer y tudalennau6
StatwsCyhoeddwyd - 2007
Cyhoeddwyd yn allanolIe
DigwyddiadInternational MultiConference of Engineers and Computer Scientists 2007, IMECS 2007 - Kowloon, Hong Kong
Hyd: 21 Maw 200723 Maw 2007

Cyfres gyhoeddiadau

EnwLecture Notes in Engineering and Computer Science
ISSN (Argraffiad)2078-0958

Cynhadledd

CynhadleddInternational MultiConference of Engineers and Computer Scientists 2007, IMECS 2007
Gwlad/TiriogaethHong Kong
DinasKowloon
Cyfnod21/03/0723/03/07

Dyfynnu hyn