Synthesizing the F8 cryptographic algorithm for programmable devices

Recently, hardware designers have been showing considerable attention to high-level parallelization and hardware synthesis methodologies. State-of-the-art approaches has benefited from the emergence of modern high-density Field-programmable Gate Arrays (FPGAs). In this paper, we explore the effectiveness of a formal methodology in the design of parallel versions of the F8 cryptographic algorithm. The suggested methodology adopts a functional programming notation for specifying algorithms and for reasoning about them. The parallel behavior of the specification is then derived and mapped onto hardware. Several parallel F8 implementations are developed with different performance characteristics. The refined designs are tested under Celoxica's RC-1000 reconfigurable computer with its 2 million gates Virtex-E FPGA. Performance analysis and evaluation of the proposed implementations are included.