Synthesis of multi-level pipelines for programmable logic devices

Recently, hardware and software engineers have been showing considerable attention to high-level parallelization and hardware synthesis methodologies. State-of-the-art approaches have benefited from the emergence of modern highdensity Field Programmable Gate Arrays. In this paper, we explore the effectiveness of a formal methodology in the design of pipelined versions of a matrix multiplication algorithm. The suggested methodology adopts a functional programming notation for specifying algorithms and for reasoning about them. The parallel behavior of the specification is then derived and mapped onto hardware. Several pipelined implementations are developed with different performance characteristics. The refined designs are tested under Agility's RC-1000 reconfigurable computer with its 2 million gates Virtex-E FPGA. Performance analysis and evaluation of the proposed implementations are presented in comparison with an Intel Core 2 DUO processor.