Serpent cryptography on static and dynamic reconfigurable hardware

This paper presents parallel reconfigurable hardware implementations of the Serpent (AES Finalist) cryptographic algorithm. Currently, Serpent is well known to be a simple but very strong encryption algorithm. The use of such an algorithm within critical applications, such as banking and military, requires efficient and highly reliable hardware implementation. We will stress the affordability of such requirements by analyzing and evaluating parallel Serpent implementations using static and dynamic reconfigurable systems. The used systems are the MorphoSys dynamically reconfigurable computer and The RC-1000 statically reconfigurable system from Celoxica Ltd with its 2 million gates Xilinx Virtex-E FPGA. In this paper, different designs for the Serpent corresponding to different Degrees of parallelism are presented. Moreover, implementation, realization, and performance analysis and evaluation of the mapped designs are included.