TY - GEN
T1 - Reconfigurable hardware implementation of the successive overrelaxation method
AU - Kasbah, Safaa J.
AU - Haraty, Ramzi A.
AU - Damaj, Issam W.
PY - 2008
Y1 - 2008
N2 - In this chapter, we study the feasibility of implementing SOR in reconfigurable hardware.We use Handel-C, a higher level design tool, to code our design, which is analyzed, synthesized, and placed and routed using the FPGAs proprietary software (DK Design Suite, Xilinx ISE 8.1i, and Quartus II 5.1). We target Virtex II Pro, Altera Stratix, and Spartan3L, which is embedded in the RC10 FPGA-based system from Celoxica. We report our timing results when targeting Virtex II Pro and compare them to software version results written in C++ and running on a general purpose processor (GPP).
AB - In this chapter, we study the feasibility of implementing SOR in reconfigurable hardware.We use Handel-C, a higher level design tool, to code our design, which is analyzed, synthesized, and placed and routed using the FPGAs proprietary software (DK Design Suite, Xilinx ISE 8.1i, and Quartus II 5.1). We target Virtex II Pro, Altera Stratix, and Spartan3L, which is embedded in the RC10 FPGA-based system from Celoxica. We report our timing results when targeting Virtex II Pro and compare them to software version results written in C++ and running on a general purpose processor (GPP).
UR - https://www.scopus.com/pages/publications/79957463756
U2 - 10.1007/978-0-387-74905-1_32
DO - 10.1007/978-0-387-74905-1_32
M3 - Conference contribution
AN - SCOPUS:79957463756
SN - 9780387749037
T3 - Lecture Notes in Electrical Engineering
SP - 453
EP - 466
BT - Advances in Industrial Engineering and Operations Research
T2 - International Multi-Conference of Engineers and Computer Scientists, IMECS 2007
Y2 - 21 March 2007 through 23 March 2007
ER -