Parallel AES development for programmable devices

With the richness of present-day hardware architectures, research effort has been going into tightening the revealed synergy between hardware and software. A large focus has been put on the creation of software tools to facilitate hardware design. Moreover, enormous efforts have been invested to develop high-level methodologies, formal techniques, parallelization procedures, and synthesis tools that target state-of-the-art hardware architectures including Field-programmable Gate Arrays (FPGAs). In this paper, we explore the effectiveness of a formal methodology in the design of parallel versions of the current Advanced Encryption Standard {AES), namely, the Rijndael cryptographic algorithm. The suggested methodology adopts a functional programming notation for specifying algorithms and for reasoning about them. The parallel behavior of the specification is then derived and mapped onto hardware. Several parallel AES implementations are developed with different performance characteristics. The refined designs are tested under Celoxica's RC-1000 reconfigurable computer with its 2 million gates Virtex-E FPGA. Performance analysis and evaluation of the proposed implementations are included.