Optimizing fir-filter mapping on the morphosys reconfigurable system

This article proposes an optimized mapping of the FIR-filter algorithm that enhances the rate of a reconfigurable computer over a basic mapping previously proposed. It also presents a new interconnection scheme in the reconfigurable part of MorphoSys, a reconfigurable computing (RC) system. RC is introduced, followed by the MorphoSys RC system. Two optimized FIR mappings that deliver enhanced speed are then presented. A spreadsheet model details the modification and the improvement. The speedup achieved is also explained, as well as the advantages in the mapping of the application.