Optimized FFT Designs for High-Performance LTE and 5G Networks

This paper proposes a run-time reconfigurable butterfly structure capable of simultaneously performing Radix-8, Radix-4, Radix-3, and Radix-2 Fast Fourier Transform (FFT) computations to cater to the bandwidth requirements of current Long-Term Evolution (LTE), Fifth Generation (5G), and beyond systems. While LTE and 5G promise exceptionally high throughput, ranging from 300 Mbps to 3 Gbps, Field-Programmable Gate Array (FPGA) and Application Specific Integrated Circuit vendors face significant challenges in meeting these demands. Efficient implementation strategies are essential for realizing these standards in silicon. Given that FFT is the cornerstone of 5G systems, its computational complexity poses challenges in meeting high throughput requirements. Furthermore, the flexibility to adapt to different bandwidths is crucial in 5G networks. Therefore, a configurable FFT engine that optimizes resource utilization while providing high throughput is highly desirable. This paper presents two FFT architectures based on the proposed reconfigurable butterfly, offering designers the flexibility to choose the most suitable approach for realizing efficient and high-throughput solutions tailored to the requirements of 5G and beyond.