High speed hardware implementation of a heuristic 2D rectangle placement algorithm

Amina Y. Maarouf; Issam W. Damaj

doi:10.1109/aiccsa.2006.205098

High speed hardware implementation of a heuristic 2D rectangle placement algorithm

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Many areas of industry involve computationally intensive layout design problems. A high performance computing system for swiftly generating and analyzing layout alternatives is much desired. The performance of such a system is largely affected by the efficiency of the placement algorithm and its degree of parallelism, and the employed hardware platform. In this paper, we present parallelization and high speed hardware implementation of a heuristic 2D rectangle placement algorithm. A performance analysis and evaluation of the suggested mapping onto reconfigurable hardware is also presented.

Iaith wreiddiol	Saesneg
Teitl	IEEE International Conference on Computer Systems and Applications, 2006
Cyhoeddwr	Institute of Electrical and Electronics Engineers (IEEE)
Tudalennau	255-261
Nifer y tudalennau	7
ISBN (Argraffiad)	1424402123, 9781424402120
Dynodwyr Gwrthrych Digidol (DOIs)	https://doi.org/10.1109/aiccsa.2006.205098
Statws	Cyhoeddwyd - 18 Ebr 2006
Cyhoeddwyd yn allanol	Ie
Digwyddiad	IEEE International Conference on Computer Systems and Applications, 2006 - Sharjah, Yr Emiraethau Arabaidd Unedig Hyd: 8 Maw 2006 → 8 Maw 2006

Cyfres gyhoeddiadau

Enw	IEEE International Conference on Computer Systems and Applications, 2006

Cynhadledd

Cynhadledd	IEEE International Conference on Computer Systems and Applications, 2006
Gwlad/Tiriogaeth	Yr Emiraethau Arabaidd Unedig
Dinas	Sharjah
Cyfnod	8/03/06 → 8/03/06

Mynediad at Ddogfen

10.1109/aiccsa.2006.205098

Ffeiliau eraill a chysylltiadau

Dolen i’r cyhoeddiad yn Scopus

Dyfynnu hyn

Maarouf, A. Y., & Damaj, I. W. (2006). High speed hardware implementation of a heuristic 2D rectangle placement algorithm. Yn IEEE International Conference on Computer Systems and Applications, 2006 (tt. 255-261). erthygl 1618363 (IEEE International Conference on Computer Systems and Applications, 2006). Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.1109/aiccsa.2006.205098

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title = "High speed hardware implementation of a heuristic 2D rectangle placement algorithm",

abstract = "Many areas of industry involve computationally intensive layout design problems. A high performance computing system for swiftly generating and analyzing layout alternatives is much desired. The performance of such a system is largely affected by the efficiency of the placement algorithm and its degree of parallelism, and the employed hardware platform. In this paper, we present parallelization and high speed hardware implementation of a heuristic 2D rectangle placement algorithm. A performance analysis and evaluation of the suggested mapping onto reconfigurable hardware is also presented.",

author = "Maarouf, \{Amina Y.\} and Damaj, \{Issam W.\}",

year = "2006",

month = apr,

day = "18",

doi = "10.1109/aiccsa.2006.205098",

language = "English",

isbn = "1424402123",

series = "IEEE International Conference on Computer Systems and Applications, 2006",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

pages = "255--261",

booktitle = "IEEE International Conference on Computer Systems and Applications, 2006",

note = "IEEE International Conference on Computer Systems and Applications, 2006 ; Conference date: 08-03-2006 Through 08-03-2006",

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Maarouf, AY & Damaj, IW 2006, High speed hardware implementation of a heuristic 2D rectangle placement algorithm. yn IEEE International Conference on Computer Systems and Applications, 2006., 1618363, IEEE International Conference on Computer Systems and Applications, 2006, Institute of Electrical and Electronics Engineers (IEEE), tt. 255-261, IEEE International Conference on Computer Systems and Applications, 2006, Sharjah, Yr Emiraethau Arabaidd Unedig, 8/03/06. https://doi.org/10.1109/aiccsa.2006.205098

High speed hardware implementation of a heuristic 2D rectangle placement algorithm. / Maarouf, Amina Y.; Damaj, Issam W.
IEEE International Conference on Computer Systems and Applications, 2006. Institute of Electrical and Electronics Engineers (IEEE), 2006. t. 255-261 1618363 (IEEE International Conference on Computer Systems and Applications, 2006).

Allbwn ymchwil: Pennod mewn Llyfr/Adroddiad/Trafodion Cynhadledd › Cyfraniad mewn cynhadledd › adolygiad gan gymheiriaid

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AB - Many areas of industry involve computationally intensive layout design problems. A high performance computing system for swiftly generating and analyzing layout alternatives is much desired. The performance of such a system is largely affected by the efficiency of the placement algorithm and its degree of parallelism, and the employed hardware platform. In this paper, we present parallelization and high speed hardware implementation of a heuristic 2D rectangle placement algorithm. A performance analysis and evaluation of the suggested mapping onto reconfigurable hardware is also presented.

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DO - 10.1109/aiccsa.2006.205098

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AN - SCOPUS:33750828628

SN - 1424402123

SN - 9781424402120

T3 - IEEE International Conference on Computer Systems and Applications, 2006

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BT - IEEE International Conference on Computer Systems and Applications, 2006

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Maarouf AY, Damaj IW. High speed hardware implementation of a heuristic 2D rectangle placement algorithm. Yn IEEE International Conference on Computer Systems and Applications, 2006. Institute of Electrical and Electronics Engineers (IEEE). 2006. t. 255-261. 1618363. (IEEE International Conference on Computer Systems and Applications, 2006). doi: 10.1109/aiccsa.2006.205098