TY - JOUR
T1 - FracTCAM
T2 - Fracturable LUTRAM-Based TCAM Emulation on Xilinx FPGAs
AU - Zahir, Ali
AU - Khattak, Shadan Khan
AU - Ullah, Anees
AU - Reviriego, Pedro
AU - Muslim, Fahad Bin
AU - Ahmad, Waleed
N1 - Publisher Copyright:
© 1993-2012 IEEE.
PY - 2020/10/8
Y1 - 2020/10/8
N2 - In this brief, we present FracTCAM, an efficient methodology for ternary content addressable memory (TCAM) emulation on Xilinx field-programmable gate arrays (FPGAs) by leveraging primitive architectural resources. The proposed methodology exploits the fracturable nature of lookup table random access memories (LUTRAMs) and built-in slice flip-flops for deeper pipelining. Multiple slices can be combined together to build deeper and wider TCAMs using ANDing operations. This results in TCAM implementations that achieve lower resources utilization, lower delay, and power consumption. A comparison with the existing schemes shows that FracTCAM consistently achieves the best performance per area (PA) and performance per area per watt (PAW).
AB - In this brief, we present FracTCAM, an efficient methodology for ternary content addressable memory (TCAM) emulation on Xilinx field-programmable gate arrays (FPGAs) by leveraging primitive architectural resources. The proposed methodology exploits the fracturable nature of lookup table random access memories (LUTRAMs) and built-in slice flip-flops for deeper pipelining. Multiple slices can be combined together to build deeper and wider TCAMs using ANDing operations. This results in TCAM implementations that achieve lower resources utilization, lower delay, and power consumption. A comparison with the existing schemes shows that FracTCAM consistently achieves the best performance per area (PA) and performance per area per watt (PAW).
KW - Field-programmable gate array (FPGA)
KW - packet classification
KW - partial reconfiguration
KW - ternary content addressable memories (TCAMs)
UR - http://www.scopus.com/inward/record.url?scp=85097336353&partnerID=8YFLogxK
U2 - 10.1109/TVLSI.2020.3026840
DO - 10.1109/TVLSI.2020.3026840
M3 - Article
AN - SCOPUS:85097336353
SN - 1063-8210
VL - 28
SP - 2726
EP - 2730
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 12
M1 - 9217507
ER -