Design and simulation of a lumped element metal finger capacitor for RF-CMOS power splitters

M. J. Uddin, A. N. Nordin, M. I. Ibrahimy, M. B.I. Reaz

Allbwn ymchwil: Pennod mewn Llyfr/Adroddiad/Trafodion CynhadleddCyfraniad mewn cynhadleddadolygiad gan gymheiriaid

1 Dyfyniad (Scopus)

Crynodeb

Design, development and simulation results of an interdigitated metal-fingers capacitors in 0.18μm RF-CMOS technology that are exploiting both lateral and vertical metal-metal capacitances are presented. Two RF-CMOS capacitors are designed specifically for applications in a 2.45GHz power splitter circuit. Five metal RF-CMOS layers are used to design two capacitors of 1.39pF and 2.2pF, consisting of 101 and 105 metal fingers respectively. The real impedance obtained at the input is Z1 = 35.04Ω and Z 2 = 39.73Ω, while the insertion loss is S21 = 2.47dB. Return loss S11 and S22 are simulated as 4.042dB and 4.047dB respectively. Phase measurements of 110.9° and 101.2° are obtained for the input and output ports, indicating that the phase shift is not degraded too much due to the capacitor.

Iaith wreiddiolSaesneg
TeitlProceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
Tudalennau284-287
Nifer y tudalennau4
Dynodwyr Gwrthrych Digidol (DOIs)
StatwsCyhoeddwyd - 27 Mai 2011
Cyhoeddwyd yn allanolIe
Digwyddiad2010 Asia Pacific Conference on Circuit and System, APCCAS 2010 - Kuala Lumpur, Malaisia
Hyd: 6 Rhag 20109 Rhag 2010

Cyfres gyhoeddiadau

EnwIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Cynhadledd

Cynhadledd2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
Gwlad/TiriogaethMalaisia
DinasKuala Lumpur
Cyfnod6/12/109/12/10

Dyfynnu hyn