Co-designs of parallel Rijndael

Issam W. Damaj

doi:10.1109/ISSOC.2011.6089220

Co-designs of parallel Rijndael

Issam W. Damaj^*

^*Awdur cyfatebol y gwaith hwn

Allbwn ymchwil: Pennod mewn Llyfr/Adroddiad/Trafodion Cynhadledd › Cyfraniad mewn cynhadledd › adolygiad gan gymheiriaid

1 Dyfyniad (Scopus)

Crynodeb

State-of-the-art Field Programmable Gate Arrays (FPGAs) have inspired the innovation of hardware/software co-design methodologies that provide a high-level of abstraction in the design process. In this paper, we explore the effectiveness of a formal methodology in the co-design of parallel versions of the Rijndael cryptographic algorithm. The investigated methodology employs the functional paradigm for specifications, derived concurrency, and hardware mapping. Several implementations are developed with different performance characteristics. The refined designs are tested under RC-1000 reconfigurable computer with its two million gates FPGA.

Iaith wreiddiol	Saesneg
Teitl	2011 International Symposium on System on Chip, SoC 2011
Tudalennau	72-77
Nifer y tudalennau	6
Dynodwyr Gwrthrych Digidol (DOIs)	https://doi.org/10.1109/ISSOC.2011.6089220
Statws	Cyhoeddwyd - 1 Rhag 2011
Cyhoeddwyd yn allanol	Ie
Digwyddiad	13th International Symposium on System-on-Chip, SoC 2011 - Tampere, Y Ffindir Hyd: 31 Hyd 2011 → 2 Tach 2011

Cynhadledd

Cynhadledd	13th International Symposium on System-on-Chip, SoC 2011
Gwlad/Tiriogaeth	Y Ffindir
Dinas	Tampere
Cyfnod	31/10/11 → 2/11/11

Mynediad at Ddogfen

10.1109/ISSOC.2011.6089220

Ffeiliau eraill a chysylltiadau

Dolen i’r cyhoeddiad yn Scopus

Dyfynnu hyn

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abstract = "State-of-the-art Field Programmable Gate Arrays (FPGAs) have inspired the innovation of hardware/software co-design methodologies that provide a high-level of abstraction in the design process. In this paper, we explore the effectiveness of a formal methodology in the co-design of parallel versions of the Rijndael cryptographic algorithm. The investigated methodology employs the functional paradigm for specifications, derived concurrency, and hardware mapping. Several implementations are developed with different performance characteristics. The refined designs are tested under RC-1000 reconfigurable computer with its two million gates FPGA.",

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AB - State-of-the-art Field Programmable Gate Arrays (FPGAs) have inspired the innovation of hardware/software co-design methodologies that provide a high-level of abstraction in the design process. In this paper, we explore the effectiveness of a formal methodology in the co-design of parallel versions of the Rijndael cryptographic algorithm. The investigated methodology employs the functional paradigm for specifications, derived concurrency, and hardware mapping. Several implementations are developed with different performance characteristics. The refined designs are tested under RC-1000 reconfigurable computer with its two million gates FPGA.

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