Accelerating iterative solvers with reconfigurable hardware

In this chapter, we aim at increasing the usage of iterative methods in all possible fields by accelerating such solvers using Reconfigurable Hardware. To demonstrate the acceleration of these solvers, we implement the Jacobi solver on different classes of FPGAs, such as Virtex II Pro, Altera Stratix and Spartan3L. The design presented is implemented using Handel-C, a compiler with hardware output. Obtained results show that reconfigurable hardware is suitable for realizing accelerated versions of such solvers.